The speed of an LDMOS transistor is determined by the transconductance gm and the input capacitance Cin, and more specifically, the speed is proportional to gm/Cin. By reducing the capacitance without changing the transconductance, the speed is increased with no additional drawbacks assuming that the process lithography is maintained unaffected.
An improved performance using a scaled down device with a channel length shorter than the smallest mask dimensions that process lithography of today permits, has been obtained in several manners. One common method is to use a diffusion step that defines a critical length such as the channel length or the length of the gate, see e.g. the published U.S. patent application Ser. No. 20020055220 A1.